Embedded design and fabrication consulting based on FPGA and Verilog prototyping lifetime expertise


Virtex and Virtex 2 implementation of prototypes using Verilog. Nets and Pins simulation under Model Sim or the environment of your choice. PCB fabrication provided by third party fab house or your own rats nest design and routing. Gerber files are welcome as a tool to decrease customer prototyping costs.


 Equally seamless port into Altera's Stratix or Cyclone and Cyclone 2 FPGAs using Quartus platform and full-scale source code compatibility with the latest Verilog release and specific JTAG extentions for Altera. Simulation under ModelSim 6.2, final project comes with stimuli files as well as source code and compiled binaries.


 Saxo-L board test-bed development and PCB-level documentation and princinple of operation documents. Integrated ARM processor and on-the-fly FPGA upload from EEPROM or user upload via JTAG or SPI in a post-boot mode. More details about Saxo-L at KNJN